Radio frequency (RF) signals are propagated through the air in an analog format. To realize the benefits that digital processing of the signal provides, the analog RF signal must be converted into a digital format. Analog to digital converters (ADCs) periodically sample the analog RF signal and output a digital signal containing the periodic samples which are representative of the original analog RF signal. Complex analog to digital converters (CADCs) receive an analog RF signal as an input and output an in-phase (I) digital output and a quadrature (Q) digital output
A complex analog to digital converter (CADC) is described in U.S. Pat. No. 7,532,684, issued May 12, 2009, to Tietjen which is herein incorporated by reference. The CADC receives an RF input signal and outputs in-phase and quadrature digital signal outputs at baseband. The CADC includes a rate reduction system, which is comprised of a number, N, of low speed ADCs. The output of each ADC is coupled to an in-phase multiplier and a quadrature multiplier. The in-phase and quadrature multipliers are, in turn, coupled to an in-phase and quadrature summer, respectively. The complex multipliers and summers define a complex bandpass filter. The digital outputs of the ADCs are multiplied by complex filter weights and summed to convert the input RF signal to baseband using aliasing to shift the band of interest (BOI) to baseband.
More particularly, the prior art CADC described in U.S. Pat. No. 7,532,684 operates using a carrier frequency fo of the RF signal is typically in the Gigahertz (GHz) range. The input RF signal may be an X-band system having a carrier frequency of approximately 9.0 GHz, for example. The RF signal further has a signal bandwidth (BW). The RF signal is sampled at an initial effective sampling rate fs, that is equal to an integer multiple of fo. A clock phase circuit provides a clock signal to each of the N ADCs, the clock signal being time interleaved with respect to the other ADCs. The clock signals to each ADC are delayed and cause the N ADCs to sequentially sample the RF signal and output a digital sample which when taken together, represent the RF waveform sampled at the effective sampling rate. Because the N phase clock signals each sample the RF signal at a rate equal to fs/N, relatively low speed ADCs may be used. This simplifies the circuit design and allows for the use of ADCs having a larger bit word size than comparable higher speed ADCs. A complex digital bandpass filter is implemented through weighting and summing the ADC outputs to produce digital I and Q outputs at baseband.
However, imperfections in the ADCs (e.g. hardware tolerances and/or manufacturing limitations) cause the measured results to fall short of expected results. Amplitude and phase imbalances between the various ADC channels along with clock skew errors result in a distorted filter response, which in turn, reduces suppression of the negative frequency image from its expected value. Furthermore, ADC hardware introduces harmonics which may reduce the spurious free dynamic range (SFDR) to a level that is insufficient for certain high-end applications such as radar and communications. Alternative techniques and systems are desired.